I normally place the capacitors on a schematic in groups next to each chip that they are intended for, or if there's a row of three identical, small, chips on the schematic I might place a group of three decouplers at the end of the row. And then when moving to layout I do normally place the 'right' decouplers near each chip rather than just picking them up randomly - but that's purely an elegance/tidyness thing and has no effect on functionality; possibly it assists debugging to be able to find the capacitors on the schematic.Personally I find the way most schematics are drawn with respect to decoupling capacitors very frustrating. The schematic provides absoloutely no idea of which pin, or even which chip the capacitor is for.
Going back to the OP's original question:
Certainly layout needs to be done with the PCB in one window and the schematic in another, and an understanding of which connections are more or less important and hence deserving of the prime positions on the PCB. Also knowing what the software really cares about in assignments of functions to pins - you will often want to go back to the schematic and swap things around to make the layout easier, but the constraints are not obvious, particularly with PIO where it doesn't matter which GPIOs you use (because they are all programmable), but a PIO program often cares deeply about which order you have attached the pins you are using. So you can happily shift from GPIO1+GPOIO2 up to GPIO4+GPIO5, but if you swap them over then the PIO code may not work.
One thing that's really important and not yet mentioned on this thread is that current flows round loops and hence for a decoupling capacitor the "+" end and the "GND" end are equally important. We've seen so many times people posting layouts here where they've done the right thing and put a capacitor nice and close to each power pin on the RP2040 - and then connect the other end of the capacitor to some random ground track that treks half a mile around the board to get back to the ground pad on the RP2040, which is useless!
On an RP2040 design, GND is really important as it's both the power return and the reference for all the I/O signals. 3V3 on the other hand, only matters in local areas: the link from decoupling capacitor to chip is really important, but the track bringing in 3V3 to that point can be longer. The thinking here is that all the high-frequency component of power consumption has to come from the decoupling capacitors - the PSU regulator isn't fast enough, and even if it were the tracks connecting it would have too much inductance. So you can think of the chip being powered entirely by the decouplers, and the 3V3 interconnect tracks are just there to 're-fill' the decouplers after use.
Producing a good layout for RP2040 on two layers is quite hard, especially if all/most of the GPIOs are used, and if you are trying to keep the size of the overall board small. Given the relatively small cost difference, I'd recommend 4-layer for a novice - dedicate one of the upper internal layer as GND, and optionally the other inner layer as 3V3. Now all your decoupling capacitors can go close to the pin and the other end just a via hole to the GND plane, giving a very short connection to the RP2040's centre pad. With 3V3 distributed in the other internal layer, you can route the 1V1 power in the spare space under the RP2040 (between the ring of outer pads and the GND pad in the middle), leaving you just the signals to route out on the top layer and the bottom layer available for crossing over or bulk routing. But do check your finished inner layers so that overlapping via holes haven't chopped up your groundplane into islands.
If you do want to get an RP2040 layout on two layers, then you should regard it almost like a single-layer layout, with almost everything on the top side and the bottom side used just for short links where you need to cross one signal over another. The rest of the bottom side then becomes a groundplane. You have to compromise a little bit to get the power routing done - I usually put the 1V1 under the chip, and half of the 3V3, but they've got to cross somewhere so I usually end up with a short 3V3 link on the bottom (but you could equally do it the other way - 3V3 in a ring under the chip and 1V1 taking a different route). Other short links on the bottom to cross signals over each other are fine so long as they aren't next to each other and so create a zone with no through route for ground.
Statistics: Posted by arg001 — Thu Mar 21, 2024 4:52 pm