Reading from a single 32-bit value into an S register is normal as that's a 32-bit volatile read. Reading from a 32-bit memory mapped register into a 128-bit Q register, however, is kind of undefined. I don't know what you expected, but gcc seems to be doing the right thing there., unless it's trying to read all 4 registers in one go, but if that was the case it wouldn't be using S registers.
Hardware registers are not normal memory, so you can't expect to read from multiple registers at once with a single vector instruction. The expected behavior is for gcc to not optimize volatile reads. If it's not doing so then its behavior is correct. If it's optimizing multiple volatile reads to vector instructions then there's something wrong with the compiler.
I asked whether you were using volatile because originally I thought that it was gcc that was producing the code to read into the Q register, as that's really not supposed to happen.
PS: I recommend using types with defined bit sizes like uint32_t from <stdint.h> in C or <cstdint> in C++.
Hardware registers are not normal memory, so you can't expect to read from multiple registers at once with a single vector instruction. The expected behavior is for gcc to not optimize volatile reads. If it's not doing so then its behavior is correct. If it's optimizing multiple volatile reads to vector instructions then there's something wrong with the compiler.
I asked whether you were using volatile because originally I thought that it was gcc that was producing the code to read into the Q register, as that's really not supposed to happen.
PS: I recommend using types with defined bit sizes like uint32_t from <stdint.h> in C or <cstdint> in C++.
Statistics: Posted by Fridux — Thu May 16, 2024 9:34 pm